Document DE 195 29 434 A1 describes a microprocessor system with core redundancy for safety-critical regulation applications. This known microprocessor system is provided with two synchronously operated central units on one or more chips which receive the same input information and execute the same program. In this arrangement, the two central units are connected by means of separate bus systems to the read-only memory (ROM) and to the read/write memory (RAM) and also to input and output units. The bus systems are connected to one another by driver stages or bypasses which allow the two central units to jointly read and process the available data, including the test data and commands. The system allows memory space to be saved. Only one of the two central units is (directly) connected to a complete read-only memory and to a read/write memory, while the storage capacity of the second processor is limited to memory locations for test data in connection with a test data generator. Access to all data is obtained by the bypasses. This allows both central units to each execute the full program.
The document WO 2005/036285 A1 proposes an integrated circuit arrangement for motor vehicle braking systems which has a microprocessor system module, a power module for actuating the actuator system and a monitoring module with safety circuits, these modules of the integrated circuit arrangement all being arranged on a shared chip. This integrated circuit arrangement has technical means and design features for electrically decoupling the modules. Possible instances of thermal coupling between the different modules continue to be largely ignored, however.